`timescale 10ns/1ns
module serial_per_test;
wire  [3:0] out; 
reg clk,reset,en,in;
serial_per3 u1(clk,reset,en,in,out);
initial
  begin
    clk=0;
    reset=1;
    en=0;
    
    #10 reset=0;
    #50 en=1; in=1;
    #50 en=1; in=0;
    #50 en=0; in=1;
    #50 en=1; in=1;
    #50 en=1; in=0;
    #50 $stop;
  end
  initial 
  begin
  forever #10 clk=~clk;
  #2000 $stop;
  end
   initial $monitor($time, , ,"out=%b in=%b en=%b clk=%b",out,in,en,clk);
 endmodule
  